Sectorless flash memory architecture
US6662263B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Mar 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased; after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory. A single erase count for an array can be used in selection of operating parameters such as voltages used during accesses of memory cells in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.