User configurable memory system having local and global memory blocks
US6662285B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.