Converting short branches to predicated instructions
US6662294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30174
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and method of processing instructions therein are disclosed. Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence within the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor. Detecting the short branch sequence may include calculating the relative branch address associated with the conditional branch instruction and comparing the relative branch address to a specified maximum. In one embodiment, the received sequence of instructions may be converted into an instruction group by the processor. In this embodiment, the specified maximum …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.