System and method for multiple cycle capture of chip state
US6662313B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318522
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.