Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer
US6662348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well, spread out the cells are in the placement. Other component functions are wire-length, which measures total linear wire-length, delay, which measures circuit timing, and power, which measures circuit power consumption. The barrier metric penalizes placements…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.