Gate structure with high K dielectric
US6664160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Nov 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.