Method for forming device isolation layer of a semiconductor device
US6664170B1 · kind B1 · utility
1Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2003 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jan 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for forming a device isolation layer of a semiconductor device by a shallow trench isolation (STI). In the disclosed methods, after a nitride layer is removed from the silicon substrate, an amorphous silicon layer is deposited thereon and is oxidized to form an amorphous spacer at a side wall of the device isolation layer by etching the amorphous silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.