Method for forming damascene metal gate
US6664195B2 · kind B2 · utility
8Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.