Flip chip C4 extension structure and process
US6664637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jan 8, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body. A portion of the first conductive body is coated with a material that is nonsolderable and nonconductive. The melting point of the first conductive body is higher than the melting point of the second conductive body. The first and second conductiv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.