Repeater for buffering a signal on a long data line of a programmable logic device
US6664807B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.