Programmable delay compensation circuit
US6665230B1 · kind B1 · utility
14Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.