Steven Shrader
18Patents
8h-index
17Co-inventors
65Inventor score
Filing activity: Jun 23, 1998 → Sep 28, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7100002B2 | Port independent data transaction interface for multi-port devices | Physics | 97 | Expired |
| US6397293B2 | Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface | Physics | 55 | Expired |
| US6230240A | Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface | Physics | 46 | Expired |
| US7054968B2 | Method and apparatus for multi-port memory controller | Physics | 25 | Expired |
| US7062625B1 | Input/output cells for a double data rate (DDR) memory controller | Physics | 23 | Expired |
| US6647516B1 | Fault tolerant data storage systems and methods of operating a fault tolerant data storage system | Physics | 15 | Expired |
| US6665230B1 | Programmable delay compensation circuit | Electricity | 14 | Expired |
| US9448883B1 | System and method for allocating data in memory array having regions of varying storage reliability | Physics | 13 | Active |
| US7299324B2 | Reactive placement controller for interfacing with banked memory storage | Physics | 6 | Expired |
| US6801954B1 | Method and apparatus to concurrently operate on multiple data movement transactions in a disk array subsystem | Physics | 5 | Expired |
| US8438325B2 | Method and apparatus for improving small write performance in a non-volatile memory | Physics | 4 | Active |
| US7143315B2 | Data storage systems and methods | Physics | 2 | Expired |
| US8201058B2 | Method and apparatus for parallel ECC error location | Electricity | 2 | Active |
| US8627169B2 | Method and apparatus for dynamically configurable multi level error correction | Electricity | 1 | Active |
| US9703625B1 | Method and apparatus for detecting or correcting multi-bit errors in computer memory systems | Physics | 1 | Active |
| US8099567B2 | Reactive placement controller for interfacing with banked memory storage | Physics | 1 | Active |
| US7574573B2 | Reactive placement controller for interfacing with banked memory storage | Physics | 1 | Active |
| US10254987B2 | Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.