Method and system for quantifying the integrity of an on-chip power supply network

US6665843B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Roland Frech · Esslingen am Neckar, DE
• Andreas Huber · Holzgerlingen, DE
• Erich Klink · Schenefeld, DE
• Jochen Supper · Herrenberg, DE

Key dates

• Filing date: Jan 18, 2002
• Grant date: Dec 16, 2003
• Expiry date: May 17, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/367
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.