Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
US6667518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Aug 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.