FPGA lookup table with transmission gate structure for reliable low-voltage operation
US6667635B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.