System and method for identification of faulty or weak memory cells under simulated extreme operating conditions
US6667917B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for identifying faulty and weak memory cells is provided. A normal internal clock signal for use in accessing a memory array is provided, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, a test is performed on the memory array using a stress clock signal. Each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. In this manner, memory cells that fail the test using the stress clock signal are identified as non-usable memory cells. In some embodiments, the normal internal clock signal is based on required read and write times for the memory cells of the memory array and a margin added to the required read and write times. Each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.