Memory system for increased bandwidth
US6668313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Apr 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.