Microengine for parallel processor architecture
US6668317B1 · kind B1 · utility
121Cited by
17References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.