Semiconductor integrated circuit with memory redundancy circuit
US6668344B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 1999 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprising a redundancy circuit having a small area and high repair efficiency in which time required to store the address of a defect is short and which can reduce the manufacturing cost of the device is disclosed. Repairing addresses are sorted and stored in accordance with a specific order. In case of storing four addresses for eight addresses, a set SFG of fuses corresponding to eight decoded addresses DA0 to DA7 is provided and information indicative of the ordinal position of the fuse in the corresponding fuse-decision results which are logic 1 is used to associate the address with the repair-decision result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.