Built-in self-testing for embedded memory
US6668347B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a central built-in self-test unit (BIST) that uses internal scan chains for testing embedded memory modules. The embedded memory modules receive address and data signals from a set of input flip-flops configured to form a scan chain. The BIST is coupled to an input scan chain and includes a pattern generator to shift a test pattern into the input scan chain for testing the embedded memory modules. Output flip-flops capture data from the embedded memory modules are also configured as a scan chain. The BIST includes address control logic to bypass the normal addressing logic of the embedded memory module when the BIST operates is operating in a memory test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.