Dual threshold gate array or standard cell power saving library circuits
US6668358B2 · kind B2 · utility
34Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.