Method of fabricating a CDBGA package
US6670219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CDBGA package comprises a thermal dissipating substrate and a plurality of conductive bumps. A plurality of vias are formed on a circuit substrate and correspond to the conductive bumps. A plurality of ground pads, ball pads and nodes are formed on the circuit substrate, wherein the ground pads are located in the vias. A solder mask layer covers the patterned trace layer. A plurality of bonding pads are formed on a chip and are electrically connected to the nodes. A molding compound encapsulates the chip, nodes and bonding pads. A plurality of solder balls are located on the ground pads and ball pads, wherein the solder balls fill the vias and are electrically connected to the conductive bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.