Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith
US6671839B1 · kind B1 · utility
56Cited by
5References
70Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.