Multi-layer circuit assembly and process for preparing the same
US6671950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a multi-layer circuit assembly is provided comprising the following steps:(a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);(b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core;(c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core;(d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and(e) applying a resinous photosensitive layer to the metal layer.Additional processing steps such as circuitization may be included.Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.