Wafer-interposer using a ceramic substrate
US6673653B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | May 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.