Field coupled power MOSFET bus architecture using trench technology
US6673680B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | May 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A power metal oxide semiconductor-field-effect-transistor (MOSFET) device using trench technology to achieve a reduced-mask-production process. The power MOSFET device includes a gate signal bus having multiple gate trenches formed using fewer masks than previously required for a similar device. The two-dimensional behavior of the trenches provides an advantageous field-coupling effect that suppresses hot-carrier generation without the need for the commonly used thick layer of silicon dioxide beneath the gate polysilicon. The use of easily controlled silicon trench etching in production of the power MOSFET results in stable, low cost, and high yielding manufacturing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.