Process for forming MOS-gated power device having segmented trench and extended doping zone

US6673681B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Christopher Boguslaw Kocon · Mountain Top, US
• Thomas E. Grebs · Smethport, US
• Joseph L. Cumbo · West Wyoming, US
• Rodney S. Ridley · Scarborough, US

Key dates

• Filing date: Jun 19, 2002
• Grant date: Jan 6, 2004
• Expiry date: Jun 19, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.