Method of fabricating an integrated circuit

US6673703B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Olivier Menut · Saint-Martin-d'Hères, FR
• Herve Jaouen · Meylan, FR

Key dates

• Filing date: Jun 13, 2002
• Grant date: Jan 6, 2004
• Expiry date: Jun 13, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/051

Abstract

A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.