Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric
US6674110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2002 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Mar 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single transistor (“1T”) ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition (“MOCVD”) or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO2, which makes it particularly suitable for a 1T cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.