Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operating
US6674684B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.