Multi-processor computer system with cache-flushing system using memory recall
US6675262B1 · kind B1 · utility
6Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Apr 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.