Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
US6675266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.