Method and apparatus for coordinating memory operations among diversely-located memory components
US6675272B2 · kind B2 · utility
164Cited by
5References
28Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 24, 2001 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.