System and method for employing a global bit for page sharing in a linear-addressed cache
US6675282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2003 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Feb 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.