Hardware device for parallel processing of any instruction within a set of instructions
US6675291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Apr 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.