Method for controlling timing in reduced programmable logic devices
US6675309B1 · kind B1 · utility
130Cited by
6References
10Claims
0Family size
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Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Jan 6, 2004 |
| Priority date | — |
| Expiry date | Apr 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.