Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
US6677646B2 · kind B2 · utility
23Cited by
10References
9Claims
0Family size
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Key dates
| Filing date | Apr 5, 2002 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.