Power level detection circuit
US6677785B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2002 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary, a second voltage level detector having an input coupled to the power source and outputting a second signal representative of a desired detection level, and a third voltage level detector having an input coupled to the power source and outputting a third signal representative of a lower boundary. The power level detection circuit also has a control circuit coupled to the first, second and third signals for outputting a power level detection signal if there is a change in the second signal, and when the power level is greater than the level of the third signal and less than the level of the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.