Reduced standby power memory array and method
US6678202B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2001 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing a memory array column (30) including a plurality of memory cells (10). Each memory cell (10) includes drive transistors (12). A current limiting transistor (34) is coupled to the drive transistors (12). A mode signal (38) is coupled to the current limiting transistor (34). The mode signal (38) is operable to deactivate the current limiting transistor (34). The current limiting transistor (34) is deactivated when the mode signal (38) indicates that the memory array column (30) is in a standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.