Fabrication method for vertical electronic circuit package and system
US6680218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2003 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10719
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.