Bare chip mounting method and bare chip mounting system
US6680221B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Oct 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.