Apparatus and method for generating output clock signal having controlled timing
US6680635B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit for improving the jitter index using a phase blender. The present delay locked loop circuit comprises a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, and a second delay circuit which receives an input clock signal in order to generate a second delayed input clock signal. The first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit. The second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delay circuit. A phase blending circuit receives the first and second delayed input clock signals, blends the phases of the first and second delayed input clock signals, and generates a phase blended clock signal. In addition, a phase detection circuit is provided to receive a reference clock signal and the phase blended clock signal, generate a phase push signal PUSH in the case that the phase of the phase blended clock signal is ahead of that of the reference clock signal, and generate a phase…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.