Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt
US6681280B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Jan 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.