Coherent data apparatus for an on-chip split transaction system bus
US6681283B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transactions, and a cache for storing coherent data. The coherency credit counter tracks coherent transactions pending in a memory controller, and delays coherent transactions from being placed on the bus if coherent resources are not available in the memory controller. When resources become available in the memory controller, the memory controller signals the coherency system in each of the master devices. The coherency system is coupled to a split transaction tracking and control to establish transaction ID's for each coherent transaction initiated by its master device, and presents a transaction ID along with an address portion of each coherent transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.