Integrated circuit with bonding layer over active circuitry

US6683380B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Taylor R. Efland · Richardson, US
• Donald C. Abbott · Norton, US
• Walter Bucksch · Freising, DE
• Marco Corsi · Little Elm, US
• Chi-Cheong Shen · Richardson, US
• John P. Erdeljac · Plano, US
• Louis N. Hutter · Richardson, US
• Quang X. Mai · Sugar Land, US
• Konrad Wagensohner · Moosburg an der Isar, DE
• Charles E. Williams · Dallas, US
• Milton L. Buschbom · Plano, US

Key dates

• Filing date: Jul 10, 2002
• Grant date: Jan 27, 2004
• Expiry date: Jul 10, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.