Read/write memory arrays and methods with predetermined and retrievable latent-state patterns
US6683804B1 · kind B1 · utility
6Cited by
13References
43Claims
0Family size
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Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Static read/write memory structures are provided that include predetermined latent-state patterns which can be retrieved with a latent-state retrieve process that differs somewhat from a conventional write process. The patterns are realized with threshold-voltage differences and they significantly enhance flexibility of memory allocation without increasing memory area nor significantly altering conventional read/write processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.