Dynamic reconfigurable memory hierarchy
US6684298B1 · kind B1 · utility
38Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Dec 13, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.