Sandhya Dwarkadas
14Patents
9h-index
17Co-inventors
65Inventor score
Filing activity: Mar 26, 1998 → Sep 7, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6684298B1 | Dynamic reconfigurable memory hierarchy | Emerging Cross-Sectional Technologies | 38 | Expired |
| US7490220B2 | Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals | Emerging Cross-Sectional Technologies | 36 | Expired |
| US8661204B2 | Mechanism to support flexible decoupled transactional memory | Physics | 32 | Active |
| US6341339B1 | Apparatus and method for maintaining data coherence within a cluster of symmetric multiprocessors | Emerging Cross-Sectional Technologies | 27 | Expired |
| US8180971B2 | System and method for hardware acceleration of a software transactional memory | Physics | 22 | Active |
| US7089443B2 | Multiple clock domain microprocessor | Emerging Cross-Sectional Technologies | 21 | Expired |
| US7739537B2 | Multiple clock domain microprocessor | Emerging Cross-Sectional Technologies | 21 | Active |
| US7289939B2 | Mechanism for on-line prediction of future performance measurements in a computer system | Emerging Cross-Sectional Technologies | 15 | Expired |
| US7072805B2 | Mechanism for on-line prediction of future performance measurements in a computer system | Emerging Cross-Sectional Technologies | 10 | Expired |
| US8103856B2 | Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration | Emerging Cross-Sectional Technologies | 7 | Active |
| US6834328B2 | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures | Emerging Cross-Sectional Technologies | 7 | Expired |
| USRE42213E1 | Dynamic reconfigurable memory hierarchy | General | 2 | Expired |
| US9411733B2 | Sharing pattern-based directory coherence for multicore scalability (“SPACE”) | Physics | 1 | Active |
| USRE41958E1 | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures | General | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.