Method and system for instruction length decode
US6684322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for decoding the length of a macro instruction is described. In one embodiment, the system comprises an opcode-plus-immediate logic unit to generate a first length value, the first length value comprising a length of an opcode plus a length of intermediate data. A memory-length logic unit generates a second length value, the second length value comprising a potential length of a memory displacement, the opcode-plus-immediate logic unit and memory-length logic unit operating in parallel. In addition, the system comprises a length-summation logic unit to sum the first length value and the second length value if the second length value is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.