Method to deposit a stacked high-&kgr; gate dielectric for CMOS applications
US6686212B1 · kind B1 · utility
57Cited by
8References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a layer of high-&kgr; dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.